The invention relates to high voltage semiconductor devices and the manufacturing process thereof and, in particular, to modular techniques for adding high voltage devices to an existing process flow for semiconductor devices.
Devices having higher voltage rating than existing devices are often required to be integrated on a chip of existing device to satisfy the demand of new applications. In many cases such integration of higher voltage device into existing lower voltage device requires drastic change to the proven process flow and/or conditions for manufacturing the existing lower voltage device resulting in performance deterioration of the existing lower voltage device to a degree that device models will have to be updated. To avoid the long design cycle and high cost of new technology development, efforts have been focused on techniques that require only minor changes to the existing low voltage device process conditions thus minimizing the impact to the performance of existing lower voltage device.
Generally in BCD (Bipolar CMOS DMOS) or BiCMOS (Bipolar CMOS) technologies, the highest operating voltage is limited by reach-through breakdown of a vertical structure of P to N junction. This vertical junction breakdown is a function of Epi thickness, doping concentration and junction depth. FIG. 1 shows an example of an existing device 300 formed in a semiconductor chip comprising an n-type epitaxial layer 18 having a thickness 43 disposed on a P substrate 14. Without showing the detail structure of the device 300, a number of N-wells 22 and P-wells 26 and 48 are provided in the N-Epi layer. Buried P regions 46 extend from the bottoms of N-Epi layer upward into the bottom edge of P-well 48 and merge together. Buried P regions also extend downwards into the substrate material 14, thus, providing isolation of the device 300 from the rest area of the semiconductor chip where other devices may be formed. Device 300 further comprises an N buried region 35 under the P-well 26 to prevent punch through between P-well and P substrate which limits the maximum operating voltage of the device 300. Using a certain thickness of Epi 18 and controlling the depth 45 of P-well 26 to optimize the performance of device 300, the vertical space 47 between the bottom of P-well 26 and the top of buried N region 35 limits a vertical breakdown voltage therefore limit the operating voltage of device 300 when a lateral breakdown controlling factor 49, namely the lateral distance between the buried P regions 46 and the N buried region 35, is large enough that a lateral breakdown voltage is much higher than the vertical breakdown voltage. The manufacturing process would start with the substrate material 14 then implant ions for regions 35 and 46 to be formed respectively in later steps. The epitaxial layer 18 is then disposed on top of the substrate material 14 and multiple N-wells and P-wells are formed extending downwards from the top surface of the epitaxial layer. Additional steps may be carried out to form a specific function such as a bipolar transistor or a MOSFET. In the case a higher operating voltage device is required to be integrated in a separate area on the same substrate, one method to increase P to N vertical breakdown voltage is to increase the thickness of Epi layer 18. This will affect the performance and isolation of existing device 300 if the process and condition of making device 300 remain the same.
Another method is introducing a lighter doping layer to reduce the doping concentration and shallow P well junction. For example, Hideaki Tsuchiko discloses in U.S. Pat. No. 7,019,377 an integrated circuit that includes a high voltage Schottky barrier diode and a low voltage device. The Schottky barrier diode includes a lightly doped and shallow p-well as a guard ring while the low voltage devices are built using standard, more highly doped and deeper p-wells. By using a process including lightly doped p-wells and standard p-wells and increased thickness of N-Epi, breakdown voltage, hence, maximum operating voltage of high voltage devices can be improved. Each method can improve breakdown voltage by 15V to 30V. The Schottky barrier diode using both methods can improve its breakdown voltage 30V to 60V without significantly affecting performance of other devices and structures.
Combination of both methods and device layout enable integrating high and low voltage devices on the same chip. However, these methods often have a minor affect to existing device performances. Some devices require a minor tweak to SPICE models. Especially increasing the N-Epi thickness has a certain limitation. Isolation link-up between up-diffusion of p-type buried region 46 and down-diffusion of Pwell 48 will weaken or may break up, if N-Epi thickness is significantly increased, resulting in incomplete device isolation. Therefore it is highly desirable to develop new techniques to integrate a high voltage device into a low voltage chip that require only inserting a few steps to existing low voltage process flow without impacting the performance of the low voltage device.